The invention pertains to a solid-state color image sensor device which provides improved resolution for both color and luminance information contained in an image being sensed.
A prior art solid-state color image sensor of the same general type to which the invention pertains is shown in FIG. 1 herein and described in detail in a paper by N. Ozawa et al., "Picture Quality Improvement of MOS-Type Single-Chip Color Video Camera", National Conference of the Institute of Television Engineers of Japan, pp. 83 and 84, 1982. This color image sensor device is composed of an array (matrix) M of pixels (picture elements) 9 arranged in rows and columns. Each pixel 9 includes a photosensitive element, such as a photodiode or the like, and an FET switch 10. Some of the pixels 9 are provided with filters so that their photosensitive elements are sensitive only to light of a certain color. In the example shown in FIG. 1, each row of pixels 9 has sensors sensitive to white, cyan and yellow light, indicated in the figure by W, Cy and Ye, respectively, with this pattern being repeated along the row. The pixels in alternate rows are arranged staggered with respect to the pixels of the adjacent rows. For example, the yellow-sensitive pixel 9-3 is arranged under and between pixels 9-1 and 9-2, which are sensitive to white and cyan, respectively. Of course, many more pixels would ordinarily be present in a sensor array than are shown in FIG. 1; a reduced number is illustrated only for clarity of illustration.
The array M is further composed of vertically-scanned lines 3-1, 3-2, 3-3, etc. and horizontally-scanned lines 4-1, 4-2, 4-3, etc. (Although the "vertically-scanned" lines 3-1, etc. extend in the horizontal direction in the figure and the "horizontally-scanned" lines 4-1, etc. extend in the vertical direction in the figure, they are termed "vertically-scanned" and "horizontally-scanned" lines, respectively, because the vertically-scanned lines 3-1, etc. are electronically scanned in the vertical direction in the figure and the lines 4-1, etc. are scanned in the horizontal direction in the figure during read out of the array.) The output electrodes (drains) of the FET switches 10 in each column, that is, outputs from pixels 9 which are sensitive to the same color, are coupled to the same horizontally-scanned line. The gates of all FET switches 10 in each row are connected to a corresponding one of the vertically-scanned lines 3-1, etc. A vertical shift register 1, acting through an interlace circuit 2, generates sequential activating pulses on the vertically-scanned lines 3-1, etc. in a manner to be described below. Each of the lines 3-1, etc. is connected PG,4 through a respective output FET switch 5 to one of two output lines 7 (OUTPUT 1) and 8 (OUTPUT 2). The FET switches 5 are provided in pairs with gates connected together and to a respective output 11-1, etc. from a horizontal shift register 6.
With reference now to FIG. 3, the output line 7 is connected directly to the armature of a first switch 19-1. The output line 8 is connected to a delay line 12, and thence on a line 8' to the armature contact of a second switch 19-2. Sum/difference circuits 13, 14 and 15, which may be implemented with operational amplifiers, receive inputs from the lines 7 and 8' via the switches 19-1 and 19-2. The switches 19-1 and 19-2 are operated by a drive circuit (not shown) so that, although each of lines 7 and 8' carry output signals composed of series of signal pulses provided by pixels sensitive to all four colors, the sum/difference circuit 13 receives only the white and cyan signal pulses and the sum/difference circuit 14 the white and yellow signals pulses. More specifically, the switches 19-1 and 19-2 are rotated together among labelled switch positions a, b and c in FIG. 3 for respective time periods a, b and c indicated in FIG. 2. In switch position a, the sum/difference circuit 13, for example, receives a white pulse from line 7 and no pulse from line 8', in switch position b, it receives a cyan pulse from line 7 and a white pulse from line 8', and in switch position c, it receives no pulse from line 7 and a cyan pulse from line 8'. This sequence then repeats. It may be verified in a similar fashion that the sum/difference circuit 14 receives white and yellow pulses. The sum/difference circuit 15 receives all pixel outputs.
The outputs of the sum/difference circuits 13, 14 and 15 are filtered by corresponding low-pass filters 16, 17 and 18 to effectively integrate the outputs of the sum/difference circuits 13, 14 and 15 (merging positive and negative pulses), and thus producing final output signals R (=W-Cy), B (=W-Ye) and Y (=W+Cy+Ye), which represent the red, blue and luminance components, respectively.
In operation, the vertically-scanned lines 3-1, etc. are activated by the vertical shift register 1 and the interlace circuit 2 in pairs so as to effect interlaced scanning of the array. For instance, in a first field, the lines 3-1 and 3-2 are simultaneously activated, and in a second field, the lines 3-2 and 3-3 are simultaneously activated. When, for example, the lines 3-1 and 3-2 are simultaneously activated, all FET switches 10 in the top two rows of pixels are simultaneously turned on. This causes a transfer of signal charges which have accumulated in the respective pixels, in amounts dependent upon the amount of light of the appropriate wavelength which has been received since the last read-out period, to the respective horizontal lines 4-1, etc.
After this charge transfer has occurred, the outputs 11-1, etc. of the horizontal shift register 6 are activated in sequence. At the time that the output line 11-1, for instance, is activated, the signal charges on the lines 4-1 and 4-2 are simultaneously transferred to the output lines 7 and 8. Subsequently, when the line 11-2 is activated, the signal charges on the lines 4-3 and 4-4 are transferred to the output lines 7 and 8 simultaneously. Such scanning is effected for each row of the array. While each row is being scanned, the positions of the switches 19-1 and 19-2 are sequentially changed, in synchronism with the scanning, to route the output signals from the array on lines 7 and 8' to the appropriate inputs of the sum/difference circuits 13 and 14 so that the circuit 13 receives only the white and cyan signal pulses and the circuit 14 the white and yellow signal pulses.
Although the signals present on the output lines 7 and 8 could be fed directly to the switches 19-1 and 19-2 and thence to the appropriate inputs of the sum/difference circuits 13, 14 and 15 for combining to produce the desired color information signals R, B and Y, that is, without a delay, to do so would produce an output image which would contain information in incorrect spatial positions, hence providing a reproduced image of low resolution. More specifically, the white-sensitive pixel 9-1 and yellow-sensitive pixel 9-3, for instance, although they are read out simultaneously with one another, are not located in the same column but are offset in position. Hence, to make the output signal pulses from the array M emerge in a time sequential order which corresponds to the actual positions of the pixels in the array, it is necessary to effect a delay of the output signal on line 8 from the output signal on line 7. It is for this reason that the delay line 12 is provided in the second output line 8.
The delay time of the delay line 12 should be equal to one-third a pixel-pitch scan time, that is, equal to the time it would take to scan through a distance of .lambda./3 in the array M of FIG. 1, where .lambda., the pixel pitch, is equal to the distance between centers, taken in the row direction, of two most closely adjacent pixels in adjacent rows sensitive to the same color of light. The resultant signals on lines 7 and 8' are shown in FIG. 2. It can readily be seen that the time positions of the various pulses which make up these signals correspond to the actual positions of the respective pixels in the array.
The arrangement of FIGS. 1-3 is disadvantageous in the following points. Because both the output lines 7 and 8 sequentially receive output signals representative of all three colors, and because the red color signal and blue color signal must be generated using only pairs of these, namely, white minus cyan and white minus yellow, respectively, it is necessary to provide the switches 19-1 and 19-2 between the output lines 7 and 8' and the respective inputs of the sum/difference circuits 13 and 14. These switches, and the circuits which must necessarily be provided for driving them, add circuit complexity. Also, the presence of such switches is disadvantageous in that transients are produced when the switch positions are changed, which tends to distort the color signal outputs.
Accordingly, it is an object of the present invention to provide a solid-state color image sensor device which has the advantages of improved resolution brought about by appropriately delaying certain of the output signals from the sensor array, but which does not suffer from the above-mentioned drawbacks.